1. Field of the Invention
The present invention relates to integrated circuit manufacturing and more specifically to simultaneously sorting and/or rearranging of multiple semiconductor wafers contained in a cassette.
2. Description of the Relevant Art
Semiconductor wafers used in integrated circuit manufacturing are usually stacked in slots of a cassette which holds the wafers. Wafers in a cassette typically undergo the same processing steps which is often referred to as a semiconductor "run". In some instances, however, it may be desirable to perform different processing steps on one or more wafers within a cassette. It may also be desirable to process wafers of a cassette in an order dissimilar from order used in a previous step. Therefore, wafers are sometimes split up into separate cassettes, randomized in their present cassettes, or transferred to another cassette of wafers. Movement of wafers among cassettes is generally carried out using a wafer sorter.
Wafer sorters typically handle one wafer at a time when splitting, transferring, or randomizing wafers within a cassette. In addition, conventional wafer sorters use two cassettes to randomize wafer locations within a target cassette. The wafers may be removed from a first (or target) cassette and stacked in a different order within a second cassette. Sometimes a second cassette may be unavailable, and the randomizing has to be delayed until a second cassette can be found. Because of this, a conventional wafer sort operation may take an unduly long time to complete the split, transfer or randomization operation.
It is therefore desirable that a wafer sorter be devised that handles multiple wafers at a time when splitting, transferring, or randomizing wafers of a cassette. Further, it is desirable that a wafer sorter need not require a second cassette for randomizing wafers of a cassette. A wafer sorter with these features would reduce the time required to order wafers according to the previous or subsequent processing steps. As such, the throughput needed to manufacture an integrated circuit can be reduced when the improved wafer sort characteristics are achieved.